Cadence Design Systems

Cadence is a leading provider of EDA and semiconductor IP. Our custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Our digital tools automate the design and verification of giga-scale, giga-hertz SoCs at the latest semiconductor processing nodes. Our IC packaging and PCB tools permit the design of complete boards and subsystems.

Cadence also offers a growing portfolio of design IP and verification IP for memories, interface protocols, analog/mixed-signal components, and specialized processors. And reaching up to the systems level, Cadence offers an integrated suite of hardware/software co-development platforms. In short, Cadence® technology helps customers build great products that connect the world.

Internship
Cadence Design Systems Cambridge, UK
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Background Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs, System-On-Chip devices, IP and complete systems at lower costs and with higher quality.   The Cambridge R&D office, in close partnership with Cadence R&D in Austin, Texas, is responsible for next generation Clock Tree Synthesis (CTS) technology, which is a core component of Cadence’s Innovus™ Implementation System.  The revolutionary approach builds the clock tree and optimizes the datapath at the same time, avoiding flow iterations caused by the jump from ideal clocks to propagated clocks, and delivering significant improvements in design speed and power consumption.   Opportunity We are looking to fill 3 month internship positions starting in the summer of 2019 ideally June or July . The Clock Team works closely with other groups in Cadence to provide robust, high performance tools. We have strong links with the GigaPlace, GigaOpt and NanoRoute optimization teams as well as timing infrastructure and RC extraction provided by the Tempus team. As a reflection of this, the scope for projects within the Clock Team is broad. All projects require a commitment to code efficiency, robustness and maintainability.   Possible internship projects include:   o    Pre-CTS logic placement – Top level designs contain non-trivial logic and convergence of clock signals, providing multiple timing paths from clock ports to timing endpoints. We want to explore the best location for those logic considering area, power and delay through the network. o    Optimizing added delay by gate sizing – Gate sizing provides a trade-off between area/power and delay. There is scope to use novel application of analysis techniques such as linear programming solvers to consider the impact of gate sizing. o    Post-route timing-slack-aware clock gate sizing – This is an opportunity to consider how to efficiently model and optimize the timing impact of gate sizing within a highly constrained part of the tool flow. Interns will have access to the range of Cadence tools and these projects drive their creative and combined use. Our group members are true subject experts and this internship offers a unique insight into their work and various aspects of EDA software design   Skills The group draws heavily on computer science and software engineering, yet an appreciation of algorithms and ability to identify novel solutions to complex problems is hugely important.   Required Skills and Qualifications o    Solid Software Engineering Background. Knowledge of C++ is desirable. o    Excellent Creative Analytic Problem Solving Skills o    Meticulous Attention to Detail o    Currently engaging in a Degree, Masters or PhD in Computer Science, Electrical/Electronic Engineering or Mathematics   Personality Successful candidates will be/have: o    Highly inquisitive o    A passion for excellence with a flair for detail o    Tenacious in identifying, analyzing & recommending improvements & innovations o    Excellent communicator o    Friendly and patient with high levels of technical empathy   Duration              Three month Summer internship with flexible start date
21 Mar, 2019